amzshar

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====== Ch5 Memory Hierarchy Design ======
※ The principle of locality (區域性原則) : most programs do not access all code or data uniformly


====== Ch5.2 Review of the ABCs of Caches ======

Cache
Instruction Cache / Data Cache
Unified Cache
Memory Stall Cycles / Misses per instruction / Miss Rate / Miss Penalty
Set / Direct mapping / N-way set Associative / Fully Associative
Block / Block Address / Tag field / Index field / Block offset
Valid bit
Random replacement
LRU
Write through / Write back
Dirty bit
Virtual Memory
Write stall / Write buffer / Write allocate / No-write allocate
Page
Page fault
Average Memory Access Time (AMAT)
Cache Hit / Cache Miss / Hit time
Locality (temporal/Spacial)
Access trace

公式1=>
CPU execution time = ( CPU clock cycles + Memory stall cycles ) × Clock cycle time

Memory stall cycles : CPU為了等待MEM存取時所暫停的時間.

公式2=>
Memory stall cycles = Number of miss × Miss Penalty
= IC × ( Miss / Instruction ) × Miss Penalty
= IC × ( Memory Accesses / Instruction ) × Miss Rate × Miss Penalty

EXAMPLE :
　CPI=4 , 50%屬於資料存取Load與Store,
　Miss Penalty=25, Miss rate=2%,
　若所有都在Cache命中,則快多少?
ANSWER :
保證命中 CPU execution time
　= ( CPU clock cycles + Memory stall cycles ) × Clock cycle time
　= (IC × CPI + 0 ) × Clock cycle time = IC × 1.0 × Clock cycle time

實際上 Memory stall cycles
　= IC × ( Memory Accesses / Instruction ) × Miss Rate × Miss Penalty
　= IC × ( 1 + 0.5 ) × 0.02 × 25 = IC × 0.75
=> CPU execution time
　　= (IC × CPI + IC × 0.75) × Clock cycle time
　　= IC × 1.75 × Clock cycle time
　　所以快了 1.75 倍.

公式3=>
Misses / Instruction
= ( Miss Rate × Memory Access ) / Instruction
= Miss Rate × ( Memory Access / Instruction )

所以上一個例題
Misses / Instruction = 0.02 × ( 1.5 / Instruction ) = 0.03
Memory stall cycles = Number of miss × Miss Penalty
　= IC × ( Miss / Instruction ) × Miss Penalty
　= IC × 0.03 × 25
　= IC × 0.75