amzshar

As we know, CPU includes 2 part.
One is CU (Control Unit), and the other is ALU (Arithmetics Logic Unit)
Let us design a 8-bit ALU by Belsa.

The ALU is as following :

這是我們 非同步電路設計 Project / LAB1 ，用 Balsa 語言寫一個 Wagging Shift Register

procedure srd1(input i : byte ; output o1 : byte ; output o2 : byte) is
variable x, y : byte
begin
loop
-- read channel i into register x while writing register y to channel o2
i -> x o2 <- y ;
-- read channel i into register y while writing register x to channel o1
i -> y o1 <- x
end -- end loop
end
========================================
-- SRE1.balsa : demux i1, i2 into o alternately
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]

procedure sre1(input i1 : byte ; input i2 : byte ; output o : byte) is
variable x, y : byte
begin
loop
i1 -> x o <- y ;
i2 -> y o <- x
end -- end loop
end
========================================
-- SRW8A.balsa: Multi-Stage Wagging Shift Register
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]
import [SRA1]
import [SRD1]
import [SRE1]

procedure srw8a(input i : byte ; output o : byte) is
constant n = 8
array 1..n/2 of channel c1, c2 : byte
begin
srd1(i, c1[1], c2[1])
sre1(c1[n/2], c2[n/2], o)
for i in 1..(n/2)-1 then
sra1(c1[i], c1[i+1])
sra1(c2[i], c2[i+1])
end -- end for
end

========================================
-- SRW8C.balsa: Multi-Stage Wagging Shift Register
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]
import [SRC1]
import [SRD1]
import [SRE1]

procedure srw8c(input i : byte ; output o : byte) is
constant n = 8
array 1..n/2 of channel c1, c2 : byte
begin
srd1(i, c1[1], c2[1])
sre1(c1[n/2], c2[n/2], o)
for i in 1..(n/2)-1 then
src1(c1[i], c1[i+1])
src1(c2[i], c2[i+1])
end -- end for
end

========================================

想說可以在開學前抵9學分，於是想要來暑修一下
(唉！要是以前大學那麼用功就好了～ >"< )

這次交大資工所"暑假"共開了四門課，
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課號 課程名稱 學分 開課系所 開課教師
5017 視訊壓縮 3.00 電機專 蕭旭峰
5018 資料探勘 3.00 電機專 彭文志/黃俊龍
5019 計算機運算，組織與分類 3.00 電機專 鍾崇斌
5020 非同步電路設計 3.00 電機專 陳昌居
-------------------------------

上週三(7/4) 去聽了彭教授的Data Mining(資料探勘)，覺得這是一門非常有趣的課，但是覺得兩個月內要修完，可能無法學到爐火純青的境界，所以等正課的時候再來修好了。是門需要 Databse、Statistics and Algorithm 技巧的課程。
課程綱要：
1. Introduction to data mining
2. Mining association rules
3. Data classification
4. Data warehouse and OLAP
5. Data clustering
6. Mining sequential patterns
7. mining
8. Stream data mining
9. Sensor data mining
10.Privacy data mining
... ... ... more ... ... ...
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上週六(7/7)早上 9:00~16:30 則是去聽鍾教授的"計算機運算，組織與分類"，聽說是第一次開這樣的課程。因為對姓鍾感到特別親切，而且以前也修過鍾教授的"嵌入式系統"，所以週末還是頂著大太陽去聽課。

嗯，聽了之後覺得可以複習大二到大四的計算機組織、機算機結構、數位邏輯...是門非常有廣度的課呦。

Summary :
1. Digital electronics—Semiconductor, devices, IC, and MOS electronics
2. Digitalization and digital systems
3. Combinational circuits—Fundamentals, simplification, design, and array logic
4. Sequential circuits—Fundamentals, analysis, simplification, and design
5. Computer abstractions and technology
6. Instructions: Language of the computer
7. Arithmetic for computers
8. Assessing and understanding performance
9. The processor: Datapath and control
10.Enhancing performance with pipelining
11.Computer categorization

-------------------------------

上週四(7/5)則是聽了陳教授的 Asyncronous Circuit Design，是一種不用 Clock 的電路設計，這真
是太酷了，有以下優點：Low power consumption, High operating speed, Less emission of electro-magnetic noise, Robustness towards variations in voltage, temperature,
and fabrication process parameters, Better composability and modularity,
and No clock distribution and clock skew problems。

最後，幾經考慮，決定修這個， ㄏㄏ ... (因為每個都想修 ... Orz ...

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.End.