amzshar

..

今天收到學校寄來的成績單ㄌ ...
　5134 正規語言 3學分 成績 92
　5146 論文研究 2學分 成績90
呵呵～ 真是太高興啦～～～

回想碩二上學期修 正規語言，確實花了不少時間、精力，
幾乎每天就抱著那本書 ...
每次上完課，都還不是很懂，大家頭上一堆問號 ...
K完原文書，再看講義，才漸入佳境 ...
每兩週還要想辦法 寫作業 交作業，有時候解個一題就花一個下午 ... ㄎㄎㄎ ...
但是對 演算法(Algorithm) 有興趣的，一定要修這門 ... 非常有趣 :D

聽說 交大博士班資格考 有考這門科目 ...
就知道果然是 不簡單 ...

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目前的戰績是 24 學分，剩 0 學分：
942 Embedded O.S. Design (嵌入式系統設計)
951 Operating System (作業系統)
953 Asynchronous Circuit Design (非同步電路設計)
961 Computer Architecture (計算機結構)
962 Advanced Database Management System (高等資料庫管理系統)
962 Multimedia Information System (多媒體資訊系統)
963 Computer Operations, Organization and Categorization (計算機運算與組織)
971 Formal Language (Regular Language) (正規語言)
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就剩下畢業論文ㄌ ... 要加油！

.
轉載自
http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=2641&newsdate=2008/04/22&language=E

TSMC Unveils New 40/65-Nanometer SPICE Tool Qualification ProgramIncreases SPICE Modeling Accuracy and Simulation Performance for High Performance Chip Designs

台積公司推出全新40奈米及65奈米SPICE電路模擬工具認證機制
增加高效能晶片設計SPICE電路模擬的精確度及效率

Issued by: TSMC 發佈單位 :台積公司
Issued on: 2008/04/22 發佈日期 : 2008/04/22

Hsinchu, Taiwan, R.O.C. – April 22, 2008 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today unveiled at its opening 2008 Technology Symposium a comprehensive SPICE Tool Qualification Program that drives its Design Service ecosystem partners to develop SPICE simulators with greater accuracy and higher performance.

台積公司今（22）日於美國矽谷舉行2008年第一場技術研討會，並在會中宣佈一個全備的SPICE電路模擬工具認證機制（SPICE Tool Qualification Program），進一步促進台積公司設計服務生態系統中的合作夥伴開發更高精確度及更高效率的SPICE電路模擬工具。

Targeting TSMC’s 65-, 40-nanometer (nm) and smaller geometry process technologies, the program’s benefits include improved device model accuracy, enhanced simulation efficiency, and compatibility across a wide selection of qualified SPICE simulators. The program also improves simulation accuracy, shortens transistor-level simulation cycle time, increases simulation capacity, and ultimately enables faster time-to-market and first time silicon success.

此一認證機制係針對65奈米、40奈米以及更先進的製程，能夠提昇元件模型精確度、強化模擬效率，並提供眾多通過認證且相容的SPICE電路模擬工具予客戶選擇。此外，此一機制亦能提昇電路模擬的精確度、縮短電晶體功能模擬的時間、增加電路模擬的處理量，因此最終能夠縮短客戶產品上市時程以及能夠促使首次晶片設計就能成功生產。

To address emerging nanometer effects associated with the 40nm technology and beyond, the company is introducing iSDK, interoperable SPICE Design Kit, together with the TSMC’s Model Interface (TMI), a new device modeling innovation and simulation performance improvement. Written in standard C language, iSDK with TMI is a new method for compact SPICE device modeling that is an addition to the traditional, and slower macro modeling approach. TSMC will provide iSDK through a common compiled shared library that will link directly to a vendors’ SPICE simulators.

為因應40奈米以及更先進製程所帶來的挑戰，台積公司推出結合了台積公司元件模型介面（TSMC Model Interface; TMI）的跨平台運作SPICE設計套件（Interoperable SPICE Design Kit; iSDK）；TMI是一個創新的元件模型模擬架構，能夠提高模擬的效率。相較於傳統、速度較慢且龐雜的模擬方法，結合了TMI的iSDK，是使用標準C語言編寫參數的全新方法，能使得電路模擬更為簡化。台積公司將與設計自動化工具(EDA)廠商建構資料庫共享平台，透過此一平台，晶片設計人員可以取得台積公司的iSDK，並直接連結到EDA廠商所提供的SPICE模擬工具進行模擬。

Once the SPICE simulator passes SPICE tool qualification TSMC will post a qualification report on TSMC-Online, the company’s customer only portal. Multiple EDA partners are already participating in the program including Agilent Technologies, Berkeley Design Automation, Cadence, Magma, Mentor, Simucad, and Synopsys.

EDA廠商的SPICE模擬工具在通過台積公司此一機制認證後，台積公司就會在其客戶專屬的線上客戶服務系統（TSMC Online）公告相關驗證報告。目前已經有包括Agilent Technologies、Berkeley Design Automation、Cadence、Magma、Mentor、Simucad以及Synopsys等多家公司參與此一機制。

“TSMC is the first foundry to deliver on the commitment of providing more design accuracy by proactively working with multiple EDA vendors to create and qualify interoperability between SPICE simulation technologies and the foundry’s most advanced processes technologies,” said S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.

台積公司設計建構行銷處資深處長莊少特表示：「台積公司領先專業積體電路製造服務領域，主動與多家EDA廠商合作，建立了一個整合SPICE模擬技術及最先進製程技術的跨平台運作機制，此一機制已經通過驗證，能夠成功提昇晶片設計的精確度。」

“Going beyond the traditional tool qualification program, TSMC’s Modeling Interface architecture sets a new standard in SPICE modeling accuracy and simulation efficiency. The program provides designers the ability to select qualified SPICE simulators to match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first time silicon success,” he explained.

莊資深處長進一步表示：「不同於傳統的電路模擬工具驗證機制，台積公司創新的元件模型介面架構為SPICE模擬精確度及效率設立了新的標準。透過台積公司的SPICE電路模擬工具認證機制，晶片設計人員可以根據設計需求選擇最適當且經過驗證的電路模擬工具、進一步提高設計與台積公司製程的相容性，並且能夠確保設計的精確度，使得首次晶片設計就能成功生產。」

台積公司今年在美國舉辦的技術研討會分別於美國時間4月22日在加州聖荷西、4月25日在麻塞諸塞州波士頓以及4月28日在德州奧斯汀舉行。此外，今年內台積公司也將陸續在台灣、日本及歐洲等地舉辦技術研討會。欲參加任一技術發研討會者，請至台積公司網站(www.tsmc.com)首頁報名。

About TSMC Active Accuracy Assurance Initiative
關於台積公司AAA-主動精準保證 (Active Accuracy Assurance Initiative; AAA) 機制

The TSMC AAA initiative is a broad-based program that encompasses all components of the design ecosystem. It provides standards of accuracy to all TSMC partners, including EDA tool suppliers, IP providers, library developers, and Design Center Alliance (DCA) partners. TSMC applies the same standards to tools, building blocks, and technologies, including TSMC Reference Flow 8.0, design for manufacturing (DFM) tools, process design kits (PDK), design support and backend services.

台積公司的AAA-主動精準保證機制是一個全面性的計畫，涵蓋所有設計生態環境中的環節，提供精確度標準給所有合作夥伴，包括電子設計自動化工具、矽智財及資料庫以及設計服務聯盟合作夥伴。此外，台積公司也以相同標準應用於自身的工具、矽智財及資料庫及技術，包括設計參考流程8.0版、可製造性設計工具、製程設計套件，以及設計支援及後段服務等。

About TSMC 關於台積公司
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2007 exceeded eight million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com .

台積公司是全球最大的專業積體電路製造服務公司，提供業界卓越的製程技術、以及業界最完備並且通過製程驗證的元件資料庫、矽智材、設計工具以及設計參考流程。民國九十六年所管理的總產能超過800萬片約當八吋晶圓，包括來自兩座最先進的十二吋超大型晶圓廠(晶圓十二及十四廠)、四座八吋晶圓廠(晶圓三、五、六及八廠)、一座六吋晶圓廠(晶圓二廠)，以及來自轉投資子公司美國WaferTech公司、台積電(上海)有限公司以及新加坡合資SSMC公司充沛的產能支援。台積公司係第一個推出40奈米製程的專業積體電路製造服務公司。進一步資訊請至公司網站http://www.tsmc.com.tw 查詢。

.
這禮拜的行程還蠻多ㄉ，因為交大資工這學期修了兩門主門，
(很慶幸撐到 研一 下ㄌ... ㄏㄏ)

一門是 傅心家教授 的 [多媒體資訊系統]
-> Multimedia Information System (類神經網路多媒體實驗室)

一門是 梁婷 教授的 [高等資料庫系統]
-> Advanced Database Management System (資訊擷取實驗室)

而這學期還有修 [論文研究] (就是跟教授 meeting, 非同步電路設計)
以及必修的 [專題研討] (就是共六次 禮拜六 的 Seminar 專家來演講)


中華隊賽程


所以
--- 星期一晚上 18:30：奧運棒球 中華-加拿大 ---

星期三晚上 : [論文研究]-非同步電路設計
--- 星期三晚上 18:30：奧運棒球 中華-澳洲 ---

星期四中午：參觀Boca新家 (後來取消ㄌ)
星期四晚上：[多媒體資訊系統]
--- 星期四晚上 18:30：奧運棒球 中華-南非 ---

星期五中午：隔壁部門專案上線，請吃飯 (因為我們是projectㄉ成員 :D )
星期五晚上：[高等資料庫系統]
--- 星期五晚上 18:30：奧運棒球 中華-韓國 ---

星期六早上：[專題研討]- (演講者：交大電機與控制工程系黃聖傑教授)

嗯～還蠻充實ㄉ ... XD

軟體越做越大，下載越來越多，我ㄉNotebook都裝不下ㄌ，
加上用 diggirl 跟 幹圖王 塞進來ㄉ檔案，一下暴增幾十GB ...
塞爆ㄌ我ㄉ60G 硬碟 ...Orz
於是上週 8/1(三) 在 Yahoo!奇摩拍賣標ㄌ一台
[ HITACHI 垂直寫錄 2.5" 5400轉/8M IDE 160G H.D.D. ]
放假回到桃園就收到ㄌ，真是超開心... 哈哈哈

所謂ㄉ"垂直寫入 Perpendicular Recording"
就是說傳統ㄉ硬碟不是垂直寫入ㄉ，而是長ㄉ像這樣，
Longitudinal recording aligns the data bits horizontally, parallel to the surface of the disk.



而新ㄉ技術 In contrast, perpendicular recording aligns bits vertically, perpendicular to the disk.
In this orientation materials and smaller crystalline grains can be used wherein it is harder to reverse the magnetic orientation, resulting in smaller physical bits that are still stable at room temperature.
長的就會像這樣



感覺同樣ㄉ距離，就可以塞更多ㄉ資料，讀寫頭也能以較小ㄉ距離來 Read/Write，酷ㄅ!!!
再看這張圖，比較有 feel ...


經過把玩之後，速度也有比較快，傳統ㄉ大概 Seek Time = 12 ~ 13 ms
而這顆 Seek Time = 11 ms (其實現在新ㄉ硬碟大多是這樣ㄉ速度啦～～～)

不過，比較慘ㄉ是，
因為Ghost 過來ㄉ開機速度還是一樣龜慢 ...
最後我還是重灌ㄌ O.S. ... 喵ㄉ勒 ... >.<"

因為考上交大研究所，今天中午請部門同事吃 「東京都日式料理百匯」竹北店
參考網址 ---> http://www.tokyodu.com.tw/ 感覺還不錯 ～

結果大家還真的蠻給他捧場的，前前後後來了 20 個人 ...
(奇怪，平常做事好像也沒那麼多人，大家平常都躲哪裡？ ... ~.~ )
看大家都吃的好開心的，自己也覺得很高興 ...

吃飽后，閉著眼睛去刷卡，不想去 care 價錢，
突然想到不知道誰說的："買東西不用看價錢"，這不是大家夢寐以求的嗎？
不過，可惜我還沒到這個境界 ...

最近都在講：考上要請客，這樣以後誰還敢考上啊？

就如 Laurence 常說的 ～
什麼？生日要請客！？，這樣以後誰還敢生日啊！？？？

啃，不知道在寫啥ㄌ，大概是感冒越來越嚴重ㄌ，還是去看醫生吧 ...

時間真快，3/18(日)就要考試了，
要考的是 "國立交通大學 96 學年度的碩士在職專班"
全名是"國立交通大學電機學院與資訊學院專班---資訊組"

目前有 135 個人報名這一組，(啃，還真多 ... = =" )
初試：筆試佔 30% ，資料審查：35%，複試：口試佔 35%
總共錄取 40 人，初試成績擇優直接錄取至多20名，
初試擇優40名再進行口試選20名(好像是)

希望萬能的天神可以給我三個願望：
... ... ... more ... ... ...
1. 考別人都不會，但我都會的 ;
2. 比我厲害的都缺考 ;
3. 嗯～再給我三個願望

就這樣！加油！！！

.End.

Embedded System Design Project
國立交通大學‧電機與資訊學院碩士在職專班‧94-2 嵌入式系統設計

■ Problem Statement :
Your company delivered a Windows-based application system to customers. Suppose that there are five tasks in the system, and three of them are more urgent than the other two. Let there be only three priority levels (i.e., H -> M -> L) available in Windows. As a compromise, you decided to give priority H to the three urgent tasks and priority M to the other two tasks. Priority L is left unused.


The above arrangement seems working fine. But one day your customer complained that your system usually exhibit poor performance. After some investigation, you found that the three tasks with priority H sometimes won’t give up the CPU for a very long period of time. As a result, those two tasks with priority M have no chance to be serviced by the CPU unless those tasks with priority H voluntarily relese the CPU.

Now your boss ask you to implement a resource-reservation mechanism. Under this mechanism, each application is associated with a parameter, namely, “_share”. For example, if a task is assigned to _share(100, 200) then the task requires 100 ms of CPU time every 200 ms. By adopting this concept, each application can receive its desired share of CPU, and the trouble mentaioned above could be eliminated.

To reflect the urgency of different application, parameter “_ungency” is assigned to each application. Every application can be assigned to a unique urgency level. When there are two applications contending the CPU, the applications of higher-level of urgencies always win. Furthermore, it is permitted that less urgency applications are preempted by highly urgent applications.

There are two implementation issues : First, there is no access to source code of a proprietary system like Windows, so everything you do must be transparent to the operating system. Second, there are only three different priority levels in your existing system and you have to emulate that each application could have their unique urgency levels.

■ Check list of stuff to deliver

● An application with a simple GUI, by which users can dynamically adjust parameter “_share” ans “_urgency” to applications. *Note* target applications can be any ordinary application being running in Windows, like WORD, IE, etc.

● A short document (5 pages, 12pt font, single line space) on your implementation. Describe how you emulate a number of urgency levels by using only three priority levels. Also describe how you verify that your approach is correct.